NP5 SPI 在线手册

SPI

SPI settings

The SPI parameters are to be set as follows (see also the following figure):

  • The idle level of the clock signal is low.
  • A bit value (MISO and MOSI) is made available on the rising edge of the clock signal.
  • The sampling instant is the falling edge of the clock signal.
  • The data are sent and received with the Most Significant Bit first.
  • The CS signal is low active.
  • As long as the SPI slave has not synchronized with the millisecond cycle of the SPI master, the SPI master may only transfer a message every two milliseconds.

    If the SPI is in sync with the millisecond cycle of the SPI master, the SPI master may transfer a message every millisecond.

The SPI slave can be controlled with a maximum frequency of 20 MHz.

The following figure shows the SPI signal curve:

Bus initialization

The slaves do not send valid content until a correct message has been received once from the master. Bus initialization is concluded with the first correctly received message.

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